1. Field of the Invention
The present invention relates to a semiconductor memory device for improving the precharge speed of a bit line in a precharge circuit in order to accelerate the reading and writing of data.
2. Description of the Related Art
In a semiconductor memory device such as a DRAM (dynamic random access memory), a precharge operation is carried out on the bit line pair connected to a sense amplifier at a timing cycle prior to the reading and writing of data. By accelerating the operation of this precharge, the read/write processing of data to the memory cell can be accelerated. FIG. 9 shows an example of the essential components of a circuit from the memory cell to the sense amplifier in a conventional DRAM.
In FIG. 9, the circuit that precharges each of the bit lines (BLT1-BLTn, BLN1-BLNn) of bit line pair BL1 to bit line pair BLn has the structure shown in FIG. 9, and specifically is structured by precharge drive circuit 1001 to precharge drive circuit 100q (q being a natural number), and precharge circuit SW1 to precharge circuit SWn. Respective memory cell MS1 to memory cell MSm (m being a natural number, and 2xc3x97n=m), for example, are connected to each of the bit lines (BLT1-BLTn, BLN1-BLNn) of bit line pair BL1 to bit line pair BLn.
When the data of memory cell MS1 is read, for example, the reading operation is carried according to the timing chart in FIG. 10. At this time, because the control signal PDLB1 is at L level, each of the bit lines of bit line pair BL1 to bit line pair BLn is precharged by precharge circuit SW1 to precharge circuit SWn.
First, at time t1, when a specified RAS address that indicates memory cell MS1 is input, the internal address signal output from the row address decoder circuit (not illustrated) is output, and the control signal RASB supplied externally inverts from H level to L level. Thereby, based on the input control signal RASB, at time t2 the sense amplifier selection circuit 1 outputs a control signal PDLB1 at H level to precharge drive circuit 1001 to precharge drive circuit 100q provided on the sense amplifier row associated with the specified address decoder.
In addition, at time 3, precharge drive circuit 1001 to precharge drive circuit 100q inverts each of the control signals PDL1 from H level to L level. Thereby, the charge operation of each of the bit lines of bit line pair BL1 to bit line pair BLn is completed. At this time, each of the bit lines of bit line pair BL1 to bit line pair BLn is charged, for example, to the value of Vcc/2 with respect to the power supply voltage Vcc of the memory.
Thereby, the MOS transistor that carries out the equalization of bit line pair BL1 to bit line pair BLn in precharge circuit SW1 to precharge circuit SWn is turned OFF, and the MOS transistor for the precharge power supply is turned OFF.
Additionally, at time t4, each of the bit lines of bit line pair BL1 to bit line air BLn becomes OPEN, and the inverts from L level to H level by the activation of the wordline SWL0.
As a result, when the data of H level is recorded in the memory cell MS1, the charge stored in the capacitor of the memory cell MS1 is supplied to the bit line BLT1, the voltage of bit line BLT1 rises above the precharge voltage xe2x80x9cVcc/2xe2x80x9d, and bit line BLN1 remains at precharge voltage xe2x80x9cVcc/2xe2x80x9d to act as a dummy line.
Additionally, at time t5, an internal address signal is output from a column decoder (not illustrated) based on the column address supplied externally. Thereby, specified sense amplifier SA1, sense amplifier SA2, sense amplifier SAk (k being a natural number, and n greater than k) are activated. That is, bit line BLT1 and bit line BLN1 are connected to the sense line in the sense amplifier SA1, bit line BLT2 and bit line BLN2 are connected to the sense line in the sense amplifier SA2, . . . , and bit line BLTk and bit line BLNk are connected to the sense line in the sense amplifier SAk.
Thereby, the sense amplifier SA1 increases the voltage difference between bit line BLT1 and bit line BLN1, and H level data is output to the output drive via a column switch (not illustrated) and a data amplifier (not illustrated).
Additionally, at timing t6, the control signal RASB output from a row address decoder circuit (not illustrated) inverts from L level to H level. Thereby, at time t7, sense amplifier SA1, . . . , sense amplifier SAk are inactivated, wordline SWL10 is similarly deactivated, and H level inverts to L level. Thereby, each of the bit lines of bit line pair BL1 to bit line pair BLn becomes OPEN.
Additionally, at time t8, control signal RASB inverts to H level, and thereby the sense amplifier selection circuit 1 inverts the control signal PDLB1 from H level to L level.
As a result, at time t9, precharge drive circuit 1001 to precharge drive circuit 100q invert each control signal PDL1 from L level to H level. Thereby, the MOS transistors in precharge circuit SW1 to precharge circuit SWn are turned ON, and thus each of the bit lines of bit line pair BL1 to bit line pair BLn is precharged. In addition, at time t15, the voltages of each of the bit lines of bit line pair BL1 to bit line pair BLn become Vcc/2, and the precharge is completed.
By shortening the time of the charge from time t8 to time t15, the waiting time up to the reading of the data is shortened, and the read operation can be carried out rapidly. Reducing the time to turn ON the MOS transistors in precharge circuit SW1 to precharge circuit SWn and increasing the charge current of the MOS transistors in precharge circuit SWi to precharge circuit SWn are methods that can be considered for achieving this objective.
According to this method, the channel length of the MOS transistors in the precharge circuit SW1 to precharge circuit SWn is determined by such factors as voltage, and thus enlarging the transistor width of the MOS transistors in the precharge circuit SW1 to precharge circuit SWn or increasing the channel conductance (conductance) of these MOS transistors in the ON state can be considered.
However, because the channel width of the MOS transistors used would be enlarged, the surface area of the formation region of precharge circuit SW1 to precharge circuit SWn would increase. If this is done, since precharge circuit SW1 to precharge circuit SWn are formed in regions SA provided by the sense amplifier circuits, etc., shown in FIG. 11, the result is widening the boundary portion of the limited memory cell region MS, and thus the total chip area of the semiconductor memory device is increased. Here, FIG. 11 is a concept drawing showing the structure of a DRAM using a shared sense method.
Therefore, rather than enlarging the channel width of the MOS transistors that form precharge circuit SW1 to precharge circuit SWn, increasing the drive capability of the MOS transistors forming precharge circuit SW1 to precharge circuit SWn by decreasing the rise time of the electrical potential of the gates of these MOS transistors, that is, either by accelerating the timing of the precharge start by decreasing the turn-on time of these MOS transistors, or by increasing the channel conductance by increasing the gate voltage of these MOS transistors, can be considered.
However, in the above-described semiconductor memory device, the MOS transistors of precharge drive circuit 1001 to precharge drive circuit 100q that conduct the charge current for driving the MOS transistors forming precharge circuit SW1 to precharge circuit SWn, which is to say, apply the charge to the gates of these MOS transistors, are formed by p-channel type MOS transistors PM.
In addition, precharge drive circuit 1001 to precharge drive circuit 100q are each formed on the associated cross areas CR (refer to FIG. 11). Thus, when increasing the channel width of the MOS transistor PS in attempting to reduce the turn-on time of the MOS transistors that form precharge circuit SW1 to precharge circuit SWn, increasing the surface area of the cross area CR becomes necessary.
The vicinity of the cross area CR has the structure shown in FIG. 12, which is an enlargement of the region T in FIG. 11. Specifically, the region in which the MOS transistor PM can be formed is only the n-WELL region NW of in the cross region CR. In this figure, the region PA denotes the region (a p-substrate or a p-WELL region) forming the n-channel MOS transistors. SP is the separation region that separates the n-WELL region NW and the region forming the n-channel type MOS transistors. Because of this, there is the problem that to the extent the turn-on time of the MOS transistors forming precharge circuit SW1 to precharge circuit SWn is greatly reduced, the channel width of the MOS transistors PM will increase.
In addition, when the conductance of these MOS transistor channels is increased by rising the gate voltage of the MOS transistors forming precharge circuit SW1 to precharge circuit SWn, that is, by increasing the voltage level of the control signal PDL1, the voltage of the power source connected to the sources of the MOS transistors PM in precharge drive circuit 1001 to precharge drive circuit 100q must be increased.
However, in the case that the voltage of the power source connecting the source is simply increased, the electric potential of the sources of the MOS transistors PM of the p-type dispersion layer and the n-type dispersion layer of the separation area SP that provides the specified well voltage to the n-WELL region acquires a forward bias (refer to FIG. 13), and unnecessary current flows to the p-type dispersion layer of the separation area SP via the n-WELL region NW from the source of the MOS transistor PM.
Because of this, while the voltage of the n-WELL areas NW can be made the same as that of the sources of the MOS transistors PM, sense amplifier SA1 to sense amplifier SAn are also formed in the n-WELL regions NW. Thus, when the voltage of the n-WELL region NW is raised, it becomes higher than the power source potential of the sense amplifiers, and when the capacity of the sense amplifiers is lowered, the access time of the semiconductor memory device slows.
Thus, one conception is that the n-WELL regions formed by the p-channel type MOS transistors of sense amplifier SA1 to sense amplifier SAn and the n-WELL regions formed by the MOS transistors PM in precharge drive circuit 1001 to precharge drive circuit 100q would be separately formed, and thereby the voltage of the power source connected to the n-WELL region formed by the MOS transistor PM and the source of the MOS transistor PM could be raised.
However, as described above, when the n-WELL regions of different potentials are separately formed, a separate region SP that stabilizes each potential becomes necessary, and the area of the n-WELL in the cross area CR becomes very small. This means that, as shown in FIG. 3, respective specified values that are determined by the design rules of the layout are necessary for: the distance d1 between the diffusion layer of the MOS transistor PM and the n-type diffusion layer of the separation region SP; the width d2 of the n-type diffusion layer of the separation region SP; the distance d3 between the n-type diffusion layer of the separation region SP and the edge of the n-WELL; the distance d4 between the edge of the n-WELL and the p-type diffusion layer of the separation region SP; the width d5 of the p-type diffusion layer of the separation region SP; and the distance d6 between the p-type diffusion layer of the separation region SP and the diffusion layer of the n-channel type MOS transistor NM.
As a result, a sufficient channel width of the MOS transistor PM cannot be made established, and in this MOS transistor PM, the turn-on time of the MOS transistors forming precharge circuit SW1 to precharge circuit SWn becomes slow, and the effect of raising the voltage level of the control signal PDL1 is lost.
In addition, if the area of the separated n-WELL regions is increased in order to establish a sufficient channel width for the MOS transistor PM, the cross region CR substantially widens, and the chip size of the semiconductor storage circuit increases.
In consideration of the above problems, it is an object of the present invention to provide a semiconductor memory device that does not increase the chip size, reduces the precharge time, and accelerates the cycle time for accessing the memory.
In the semiconductor memory device according to a first aspect of the present invention, a memory cell region formed from a plurality of memory cells, a plurality of word lines that select the memory cells, a word line drive circuit that, based on an externally supplied address signal, activates the word line connected to the memory designated by that address, a bit line that is connected to this memory cell and reads information stored in the memory cell selected by the activated word line as the voltage change from the specified precharge voltage, a sense amplifier that amplifies the potential difference between the bit line pairs, which are two adjacent bit lines combined together, and detects the data stored in this memory cell, a precharge circuit that precharges the potential of the two bit lines of this bit line pair connected to this sense amplifier before the word line selects the memory cell, and a precharge drive circuit that supplies a control signal of a specified H level voltage from a second n-channel type MOS transistor to a gate of an n-channel type first MOS transistor that forms this precharge circuit and supplies the precharge current to the bit line are provided, wherein the voltage of the ON signal turns ON the second MOS transistor and is input into the gate of this second MOS transistor is equal to or greater then the voltage value equal to the sum of the voltage of this control signal and the threshold value voltage of the second MOS transistor.
In a second aspect of the semiconductor memory device according to the first aspect of the present invention, a voltage transformer circuit that outputs from the internal logic circuit an H level voltage of the charge signal that turns ON the second MOS transistor is provided, and this output voltage, serving as this ON signal, is equal to or greater than the voltage value that equals the sum of the voltage of the control signal and the threshold value voltage of this second MOS transistor.
In a third aspect of the semiconductor memory device according to the first and second aspect of the present invention, the voltage of the control signal is set to a higher value that the power source voltage that is used by the internal logic circuit.
In a fourth aspect of the semiconductor memory device according to any of the first through third aspects of the present invention, before a timing cycle in which the precharge circuit carries out the precharge for the bit line pairs, the voltage transformation circuit supplies the voltage-transformed voltage to the drive circuit.
In a fifth aspect of the semiconductor memory device according to any of the first through fourth aspects of the present invention, an n-channel type third MOS transistor is provided in which a source is grounded, a drain is connected to the gate of the first MOS transistor, and the precharge stop signal having a logic reverse that of the charge signal from the prior stage of the voltage transformation circuit is input into a gate
In a sixth aspect of the semiconductor memory device according to any of the first through fifth aspects of the present invention, this precharge drive circuit is formed by the second MOS transistor and the third MOS transistor.
In a seventh aspect of the semiconductor memory device according to any of the first through sixth aspects of the present invention, at the part where the sense amplifier and the word line drive circuit intersect, there is a cross region wherein said sense amplifier, said word line drive circuit, or said memory cell are not formed, and the second MOS transistor and the third MOS transistor are formed in this cross region.
In a eighth aspect of the semiconductor memory device according to any of the first through seventh aspects of the present invention, at the part where the sense amplifier and the word line drive circuit intersect, there is a cross region wherein said sense amplifier, said word line drive circuit, or said memory cell are not formed, and the second MOS transistor is formed in one cross region, and the third MOS transistor is formed in the other cross area.
In a ninth aspect of the semiconductor memory device according to any of the first through eighth aspects of the present invention, a delay circuit is provided between the gate of the third MOS transistor and the stage before the voltage transformation circuit, wherein the propagation to the gate of the third MOS transistor of the precharge stop signal is delayed by a specified interval, that interval being only the time of the rise of the precharge stop signal.
In a tenth aspect of the semiconductor memory device according to any of the first through ninth aspects of the present invention, the channel width of the third MOS transistor is formed so as to be larger than the second channel width.